Design challenges
- Bursts above 50 W and 1000 Vpp at the antenna: a power stage with 600 V MOSFETs and a safe failure mode.
- Recovering 100 µVpp replies on the same antenna: a receive path that withstands 1000 Vpp during transmission.
- Better signal-to-noise ratio: transmit, power and digital logic kept apart from the analog chain across 6 layers.