Design challenges

1. MCU, FPGA, e-paper PMIC and charger in 65 × 49 mm: 0.4 mm-pitch BGA and QFN parts and 0201 passives on 6 layers.
2. Low power from end to end: parts with sleep modes, load switches that fully cut each block, and optimized routing.
3. Working first time with 10+ complex ICs: in-depth study of datasheets, forums and earlier designs.